(China (Mainland))
Product Summary
The MT48LC32M16A2P-75：C is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The MT48LC32M16A2P-75：C is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). The MT48LC32M16A2P-75：C provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.
Parametrics
MT48LC32M16A2P-75：C absolute maximum ratings: (1)Voltage on VDD, VDDQ Supply Relative to VSS:-1V to +4.6V; (2)Voltage on Inputs, NC or I/O Pins Relative to VSS:-1V to +4.6V; (3)Operating Temperature:0℃ to +70℃; (4)Storage Temperature (plastic):-55℃ to +150℃; (5)Power Dissipation:1W.
Features
MT48LC32M16A2P-75：C features: (1)PC100- and PC133-compliant; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge; (5)Programmable burst lengths: 1, 2, 4, 8, or full page; (6)Auto Precharge, includes concurrent auto precharge, and Auto Refresh Modes; (7)Self Refresh Mode; (8)64ms, 8,192-cycle refresh; (9)LVTTL-compatible inputs and outputs; (10)Single +3.3V ±0.3V power supply.
Diagrams
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 MT48LC32M16A2P-75:C |
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IC SDRAM 512MBIT 133MHZ 54TSOPII |
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MT48LC32M16A2P-75:C TR |
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IC SDRAM 512MBIT 133MHZ 54TSOP |
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